Staff/Sr Staff Engineer, Physical Design

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Skills you'll use

What you'll do

• Lead block- and subsystem-level physical design closure, including timing closure, congestion mitigation, power integrity, and overall physical implementation quality
• Collaborate closely with SoC-level physical design teams to align on clocking strategies, floorplanning intent, and integration requirements, without direct ownership of SoC-level execution
• Apply deep understanding of clocking methodologies to ensure subsystem-level clock domains integrate cleanly into the broader SoC clock architecture
• Develop, refine, and scale subsystem closure methodologies, flows, and automation, improving predictability, quality, and execution efficiency
• Mentor and guide physical design engineers within subsystem teams, promoting best practices, technical rigor, and methodology adoption
• Work cross-functionally with RTL design, STA, power, verification, and backend teams to ensure smooth handoffs and robust closure
• Proactively identify, assess, and mitigate physical design risks, coordinating closely with SoC teams to manage impacts and drive solutions
• 10+ years of experience in physical design, with a strong focus on subsystem-level closure for complex hierarchical SoCs
• Strong expertise in: • Timing closure and constraint management
• Congestion analysis and resolution

Who can apply

• Strong expertise in: • Timing closure and constraint management
• Congestion analysis and resolution
• Power integrity and power-aware physical implementation
• Block and subsystem-level physical design flows
• Solid understanding of SoC-level floorplanning and clocking methodologies, including: • Clock domain partitioning
• Clock tree architecture
• Hands-on experience with industry-standard tools such as: • Synopsys ICC2, Fusion Compiler, PrimeTime
• Cadence Innovus, Tempus, Certus

About Renesas Electronics

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