Staff/Senior Staff Engineer, Synthesis & Timing Constraints

About this role

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Skills you'll use

What you'll do

• Define, develop, and maintain timing constraints (SDC) at IP, subsystem, and chip levels.
• Drive RTL synthesis and optimization using Synopsys Design Compiler and Fusion Compiler.
• Analyze and resolve timing, area, power, and implementation challenges to achieve design targets.
• Collaborate with cross-functional teams to ensure robust design convergence throughout the implementation cycle.
• Develop and enhance methodologies, flows, and automation to improve productivity and design quality.
• Support timing closure activities and drive best practices for synthesis and constraint management.
• Debug and resolve synthesis and timing-related issues during project execution.
• Contribute to flow improvements for advanced-node ASIC/SoC development.
• Bachelor's or Master's degree in Electronics Engineering or Electrical Engineering.
• 10-15 years of experience in ASIC/SoC implementation.

Who can apply

• Bachelor's or Master's degree in Electronics Engineering or Electrical Engineering.
• 10-15 years of experience in ASIC/SoC implementation.
• Expert knowledge of Synopsys Design Compiler and Fusion Compiler.
• Strong understanding of Static Timing Analysis (STA), timing closure, and SDC methodology.
• Hands-on scripting experience in Tcl and/or Python.
• Experience with advanced-node implementation flows.
• Strong analytical, problem-solving, and debugging skills.
• Ability to work effectively with global cross-functional teams.

Perks & benefits

About Renesas Electronics

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