Senior Software Engineer - Dataplane High Availability & Clustering

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Skills you'll use

What you'll do

• Dataplane HA Architecture — Own fast-path HA engine design covering Active/Standby mirroring, Active/Active flow redistribution, and zero-drop VMAC/VIP failover.
• Stateful Session Mirroring — Build low-overhead dataplane sync for TCP/UDP 5-tuple tables, IPsec SA fast-path, SSL-VPN contexts, and L7 states across HA peers at line rate.
• Lock-Free Session Tables — Design NUMA-aware, lock-free (RCU/CAS/seqlock) session tables for multi-core pipelines sustaining tens of millions of concurrent sessions at sub-microsecond latency.
• High-Performance Sync Fabric — Engineer zero-copy ring buffer / DPDK mempool-based sync with prioritized queuing for IPsec/SSL-VPN state at sub-millisecond replication latency.
• Asymmetric Flow Handling — Implement cross-node packet redirect, flow pinning, and state sync for asymmetric TCP/UDP and IPsec traffic in Active/Active topologies.
• Hardware Offload Integration — Mirror offloaded SA/session state across HA peers for inline crypto engines (QAT, OCTEON, Nitrox) to preserve hardware acceleration post-failover.
• Hitless Failover & ISSU — Ensure zero packet drops, zero IPsec renegotiations, and zero TCP resets during failover and In-Service Software Upgrades.
• Technical Leadership — Drive dataplane HA architecture reviews, define benchmarks, author Specs, and mentor senior dataplane engineers.

Who can apply

• 7+ years of C/C++ development for high-performance networking dataplanes — firewalls, routers, switches, or carrier-grade appliances.
• Dataplane HA & Fast-Path — Production experience with lock-free session mirroring, Active/Active packet steering, and stateful failover at 10G–100G+ line rates.
• Packet Processing Frameworks — Deep hands-on with DPDK, ODP, OFP, or XDP/eBPF including zero-copy buffers, ring queues, and CPU core pinning.
• Protocol Fast-Path — Expertise in IPsec SA fast-path lookups, SSL-VPN encapsulation/decapsulation, and TCP/UDP conntrack state synchronization.
• Hardware Acceleration — Working knowledge of crypto offload engines (QAT, Marvell OCTEON, Cavium/Nitrox) or SmartNIC/DPU integration into packet pipelines.
• Multi-Core & NUMA — Expert in cache-line alignment, lock-free concurrency, memory barriers, and NUMA-aware data structures for packet processors.
• Debugging — Proficient with perf, GDB, ftrace, eBPF, tcpdump, and Wireshark for diagnosing dataplane race conditions and session continuity failures.

About SonicWall

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