FPGA Design Intern

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Skills you'll use

What you'll do

• Work on getting a design onto real hardware — synthesis, place-and-route, and the timing closure that decides if it runs alongside the core team
• Apply Verilog / VHDL, FPGA Design Flow, Xilinx Vivado, Timing Closure to live, production-facing problems
• Document your work clearly for reviewers and stakeholders
• Participate in reviews and act on the feedback you receive
• Collaborate across engineering, product, design or business as required
• Follow the team's quality, testing and documentation standards

Who can apply

• Pursuing or recently completed B.E./B.Tech/Diploma in Electronics, Electrical, E&TC or Instrumentation Engineering
• Graduating batch 2026 or 2027 — final-year students and recent graduates welcome
• 60% / 6.0 CGPA and above preferred; strong project work is considered alongside academics
• Working knowledge of Verilog / VHDL, FPGA Design Flow, Xilinx Vivado (or a genuine willingness to learn them)
• Exposure to Timing Closure, Digital Design, Simulation is an advantage
• Clear written and verbal communication in English, and care with detail in your work
• No prior work experience required — this is a fresher-friendly internship
• Based in Bhopal, Madhya Pradesh or willing to work from there for the internship period

Perks & benefits

Interview & selection process

3 rounds — typical selection flow for this role:

1. 1Application screening & resume shortlisting by the talent team
2. 2Technical interview on fundamentals and your projects
3. 3HR discussion — stipend, start date, expectations and offer

About Paras Defence

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