Physical Design Engineer Intern
About this internship
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Skills you'll use
What you'll do
- Work on taking a netlist through floorplan, place-and-route and timing closure alongside the core team
- Apply Logic Synthesis, Static Timing Analysis (STA), Floorplanning, Place & Route (P&R) to live, production-facing problems
- Document your work clearly for reviewers and stakeholders
- Participate in reviews and act on the feedback you receive
- Collaborate across engineering, product, design or business as required
- Follow the team's quality, testing and documentation standards
Who can apply
- Pursuing or recently completed B.E./B.Tech (ECE/EEE), M.Tech (VLSI / Microelectronics) or M.Sc (Electronics)
- Graduating batch 2026 or 2027 — final-year students and recent graduates welcome
- 60% / 6.0 CGPA and above preferred; strong project work is considered alongside academics
- Working knowledge of Logic Synthesis, Static Timing Analysis (STA), Floorplanning (or a genuine willingness to learn them)
- Exposure to Place & Route (P&R), DRC / LVS Verification, Clock Tree Synthesis is an advantage
- Clear written and verbal communication in English, and care with detail in your work
- No prior work experience required — this is a fresher-friendly internship
- Based in Coimbatore, Tamil Nadu or willing to work from there for the internship period
Perks & benefits
Interview & selection process
3 rounds — typical selection flow for this role:
- 1Application screening & resume shortlisting by the talent team
- 2Team-fit / behavioural interview with the team
- 3HR discussion — stipend, start date, expectations and offer
About Royal Enfield
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