Senior Lead Post-Silicon validation Engineer - SMMU

About this role

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Skills you'll use

What you'll do

• Own SMMU validation at block/IP and subsystem levels: coverage-driven test planning, stimulus development, checking/score boarding, and closure.
• Develop test build reusable verification components for SMMU, including page table generators, translation fault injectors, and traffic generators.
• Validate system interactions: SMMU with ARM cores, MMU/TLB, NoC/Interconnect, coherency (ACE/CHI or equivalent), and clock/reset domains (including CDC and low-power/clock-gating scenarios).
• Exercise page table formats and features: stage-1/stage-2 translations, ASIDs/VMIDs, context banks/stream IDs, MSI/IOMMU operations, address translation faults, and SVA/ATS (if applicable).
• Debug complex issues using JTAG and on-chip debug/trace infrastructure (ETM/STM/SWO), bring-up scripts, and logic analyzers; drive root cause with design/architecture teams.
• Performance & stress validation: create stress scenarios (burst/atomic/ordering/ QoS), measure bandwidth/latency, and validate backpressure & throttling behavior through NoC.
• Contribute to emulation/FPGA and post-silicon: port tests, build bare-metal validation, develop board bring-up sequences and lab automation.
• Own quality metrics: functional coverage, code coverage, assertions, defect density/escape rates; author clear test/coverage reports and sign-off criteria.
• Collaborate cross-functionally with architecture, RTL design, firmware/driver, physical design, and validation teams to refine specs and close issues quickly.
• Continuously improve methodology, tools, and checkers; mentor junior engineers in best practices.

Who can apply

• Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

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