Design Verification Intern

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Skills you'll use

What you'll do

• Work on proving a design is wrong before silicon does — coverage-driven verification, not a handful of directed tests alongside the core team
• Apply SystemVerilog, UVM, Functional Coverage, Assertions (SVA) to live, production-facing problems
• Document your work clearly for reviewers and stakeholders
• Participate in reviews and act on the feedback you receive
• Collaborate across engineering, product, design or business as required
• Follow the team's quality, testing and documentation standards

Who can apply

• Pursuing or recently completed B.E./B.Tech/Diploma in Electronics, Electrical, E&TC or Instrumentation Engineering
• Graduating batch 2026, 2027 or 2028 — final-year students and recent graduates welcome
• 60% / 6.0 CGPA and above preferred; strong project work is considered alongside academics
• Working knowledge of SystemVerilog, UVM, Functional Coverage (or a genuine willingness to learn them)
• Exposure to Assertions (SVA), Testbench Architecture, Simulation Tools is an advantage
• Clear written and verbal communication in English, and care with detail in your work
• No prior work experience required — this is a fresher-friendly internship
• Based in Chandigarh, Chandigarh or willing to work from there for the internship period

Perks & benefits

Interview & selection process

2 rounds — typical selection flow for this role:

1. 1Application screening & resume shortlisting by the talent team
2. 2Team-fit / behavioural interview with the team

About Digantara

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