VLSI Design Engineer Intern
About this internship
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Skills you'll use
What you'll do
- Work on writing and verifying RTL for real silicon blocks alongside the core team
- Apply Verilog / SystemVerilog, RTL Design, ASIC / FPGA Architecture, Cadence / Synopsys Tools to live, production-facing problems
- Document your work clearly for reviewers and stakeholders
- Participate in reviews and act on the feedback you receive
- Collaborate across engineering, product, design or business as required
- Follow the team's quality, testing and documentation standards
Who can apply
- Pursuing or recently completed B.E./B.Tech (ECE/EEE/E&I), M.Tech (VLSI / Microelectronics) or M.Sc (Electronics)
- Graduating batch 2025, 2026 or 2027 — final-year students and recent graduates welcome
- 60% / 6.0 CGPA and above preferred; strong project work is considered alongside academics
- Working knowledge of Verilog / SystemVerilog, RTL Design, ASIC / FPGA Architecture (or a genuine willingness to learn them)
- Exposure to Cadence / Synopsys Tools, Digital Logic Design, Functional Verification is an advantage
- Clear written and verbal communication in English, and care with detail in your work
- No prior work experience required — this is a fresher-friendly internship
- Based in Indore, Madhya Pradesh or willing to work from there for the internship period
Perks & benefits
Interview & selection process
4 rounds — typical selection flow for this role:
- 1Application screening & resume shortlisting by the talent team
- 2Online aptitude / domain assessment
- 3Technical interview on fundamentals and your projects
- 4HR discussion — stipend, start date, expectations and offer
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