Senior Lead Engineer - SoC Design Verification

About this role

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Skills you'll use

What you'll do

• Develop and own SoC-level and/or IP-level verification suites with coverage goals.
• Responsible for executing verification plan according to the product specification and verification requirements defined by product architects.
• Responsible for developing, debugging and running UVM based verification environment for RTL/netlist simulation.
• Define and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level, FPGA, Emulation platform), run regression, collect and analyze code/functional coverage
• Drive DV closure on diverse IPs and subsystems, ensuring maximum coverage and quality.
• Familiar with both SoC-level and IP-level verification environments.
• Collaborate with the team in developing and improving flows for maximum reuse and efficiency.
• Mentor junior team members while actively collaborating with design teams for issue resolution and sign-off.

Who can apply

• Experience: 5-12 years in SoC/IP verification with participation in successful tape-outs of SoCs.
• Technical Skills:
• Strong expertise in ARM-based microcontrollers and SoC-level verification, including C based DV.
• Proficiency in Verilog, SystemVerilog, UVM, and constrained-random verification.
• Familiarity with EDA tools (Synopsys VCS, Cadence Xcelium).
• Experience with low-power verification (UPF) is a plus.
• Gate-level simulations and power-aware simulations is a plus.
• Good working knowledge of assertions (SVA) and functional coverage.
• Verification of multiple interfaces: SPI, I²C, UART, USB, PCIe, Ethernet, CAN, eSPI is desirable.
• Knowledge of Flash memory and security IPs is nice to have.

About NXP

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