Senior Analog & Mixed-Signal Layout Design Engineer

About this role

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Skills you'll use

What you'll do

• We are seeking a highly skilled High-speed SERDES IO PHY Layout designer with 5 - 7 years of experience. Apart from Serdes PHY Layout, the ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, Automated PnR and a passion for solving challenging technical problems.

Who can apply

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field.
• 5-7 years of experience in IO/Analog mixed-signal IC layout design and block level PnR
• Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics.
• Hands-on experience with custom layout design for various analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, DDR IOs, and ESD circuits.
• Familiarity with custom digital layout (i.e. high speed logic paths).
• Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding).
• Strong understanding of analog/IO design principles, including parasitic effects.
• Aware of layout techniques to mitigate ESD, latch-up issues.
• Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 7nm and below.
• Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating.

About Sandisk

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