SR ENGINEER, DDEG Design Methodology

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Skills you'll use

What you'll do

• Actively leverage AI‑based tools, agentic workflows, and automation frameworks to:
• Accelerate verification cycle time
• Assist in Test-Case/TB and various other components required for DRAM Design Verification
• Improve debug efficiency across simulation and silicon learning loops
• Strong judgment to validate AI outputs before use (review assumptions, align with specs/standards, cross-check with simulations, waveforms, assertions, and coverage reports, and document what was accepted/changed) prior to incorporating results into design decisions, verification plans, or debug conclusions
• Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon block level/full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features.
• Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products.
• Good understanding of digital / mixed signal circuits and experience in Digital /Mixed signal Verification. Understand the usage of tools like Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice.
• Hands on experience in writing Verilog, Real Number Models is a plus.
• Hands on experience in building SV testbenches at Block and Fullchip Level.

Who can apply

• Good communication skills and ability to work well in a team
• Guide new team members and energetic engineers in the team
• Analytical capability for complex CMOS and/or gate level circuit designs
• Proficient with either SPICE and/or Verilog simulations

About Micron

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