System IP RTL Design Lead

About this role

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Skills you'll use

What you'll do

• A seasoned IP / SoC design leader with 20+ yrs of strong expertise in complex SoC architectures, high-speed protocols, and large-scale IP integration.
• Skilled in RTL design and debug (Verilog/SystemVerilog) with hands-on experience using industry-standard tools for simulation, synthesis, lint, CDC, and power analysis on high-frequency designs.
• Experienced in driving microarchitecture decisions, authoring design specifications, and performing complex PPA trade-off optimizations.
• A proactive problem solver capable of debugging complex logic across hierarchical levels within pre-silicon simulation, emulation, and post-silicon bring-up environments.
• A collaborative technical leader who can work seamlessly across architecture, design, verification, physical design, software, firmware and external IP vendors.
• Strong communication skills and the ability to mentor and guide engineering teams.
• Lead the technical definition, selection, and integration of internally and third party developed IPs including MMUs, Interrupt controllers, Interconnects, Memory controllers, and peripherals within advanced SoCs.
• Define system-level requirements, IP specifications, interfaces, and integration methodologies to achieve performance, power, and area (PPA) goals.

Who can apply

• A seasoned IP / SoC design leader with 20+ yrs of strong expertise in complex SoC architectures, high-speed protocols, and large-scale IP integration.
• Skilled in RTL design and debug (Verilog/SystemVerilog) with hands-on experience using industry-standard tools for simulation, synthesis, lint, CDC, and power analysis on high-frequency designs.
• Experienced in driving microarchitecture decisions, authoring design specifications, and performing complex PPA trade-off optimizations.
• A proactive problem solver capable of debugging complex logic across hierarchical levels within pre-silicon simulation, emulation, and post-silicon bring-up environments.
• A collaborative technical leader who can work seamlessly across architecture, design, verification, physical design, software, firmware and external IP vendors.
• Strong communication skills and the ability to mentor and guide engineering teams.
• Lead the technical definition, selection, and integration of internally and third party developed IPs including MMUs, Interrupt controllers, Interconnects, Memory controllers, and peripherals within advanced SoCs.
• Define system-level requirements, IP specifications, interfaces, and integration methodologies to achieve performance, power, and area (PPA) goals.
• Drive IP design through sign-off activities while ensuring compliance with functional, security, and quality requirements.
• Bring deep expertise in protocols and interfaces such as AXI/AHB/APB, PCIe, DDR, and USB, along with scripting and verification methodologies including Python, Tcl, UVM, and formal verification.

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