Zebu flow Engineer

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Skills you'll use

What you'll do

• The successful candidate will join SiFive's System Validation team, which is responsible for the building flow for modelling SiFive's RISC-V CPUs on Emulators like Synopsys Zebu. This role extends beyond Emulators and will work with other FPGA based platforms and flows. .
• This position offers significant exposure to RISC-V processors, the RISC-V software ecosystem, and various development boards, providing exceptional learning opportunities for engineers pursuing a career in the RISC-V domain.

Who can apply

• 1+ years of experience with a Bachelor’s or Master’s degree in Computer Science or Electronics and Communication Engineering is required.
• A strong understanding of logic design is essential.
• Prior exposure to logic design using Verilog and the subsequent porting of designs onto FPGA platforms is necessary.
• Practical experience with Linux-based operating systems and scripting languages such as Python and BASH is mandatory.
• Candidates must possess a positive attitude, a proactive approach to continuous learning, and a commitment to achieving excellence in their work.

About SiFive

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