Senior Engineer, Physical Design - Interconnects

About this role

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Skills you'll use

What you'll do

• About the Role -
• As a Senior Physical Design Engineer (Interconnects), you will be responsible for the physical design implementation of the high-speed logic that binds the SoC together. This includes scalable Network-on-Chips (NoC), coherent CPU clusters, and critical Uncore subsystems.
• In this role, you will move beyond standard block-level implementation to tackle the unique challenges of high-speed Interconnects. You will bridge the gap between RTL design and physical design, ensuring that our complex interconnect architectures achieves aggressive PPA (Power, Performance, Area) targets on the world’s most advanced process nodes.

Who can apply

• Relevant Experience: 4+ years of hands-on physical design experience, with a focus on closing high-performance blocks in FinFET nodes (7nm or below).
• System IP Knowledge: Solid understanding of SoC building blocks such as NoC architectures, coherent interconnects, or cache-coherent clusters. You should be comfortable reading RTL to understand design intent.
• Physical Implementation Skills: Mastery of hierarchical design techniques, including partitioning, timing budgeting, and multi-mode multi-corner (MMMC) timing closure.
• EDA Tool Proficiency: Strong hands-on proficiency with major EDA suites - Synopsys and/or Cadence implementation and sign-off tools.
• Analytical Mindset: A data-driven approach to optimizing PPA trade-offs, combined with the ability to communicate technical challenges clearly to the cross-functional teams.

Perks & benefits

About SiFive

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