Sr Engineer, Advanced Packaging Design Enablement Engineering (APDEE)

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Skills you'll use

What you'll do

• Build and tapeout PWF Reticles Design
• Developing DFTs in test vehicles for packaging related fail modes
• Coordinate with HIG-HBM DTPCO and HIG-HBM teams to build test structures for live die
• Design rules management, Process Design rules for PWF , wafer thinning and dicing, die stacking etc
• BEOL Design - mainly engagement with FE Integration teams
• Engage with Scribe Design team to capture Advanced Packaging requirements and Review
• TSV design engagement with HIG-HBM DTPCO teams ( electrical , thermal and mechanical performance)
• Creationand Maintenance of DFMEA related to advacned packaging process steps like PWF, die stacking etc
• Perform Electrical Simulations to understand the fail mode mechanism
• Required Qualifications

Who can apply

• ∙ Masters or PhD degree in Electrical Engineering, Computer Engineering, or related field required

About Micron

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