Senior Engineer - Physical Design

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Skills you'll use

What you'll do

• Floorplanning & Physical Implementation
• Own die-level and block-level floorplanning using Cadence Innovus or Synopsys ICC2 — defining die size, I/O ring placement, power ring topology, and macro placement strategies.
• Perform early floorplan exploration to evaluate area, aspect ratio, and pin assignment trade-offs in collaboration with the architecture and package teams.
• Plan and implement hierarchical design partitioning — define interface timing budgets, feedthrough corridors, and block-level pin constraints for clean top-level integration.
• Coordinate macro placement with memory compilers, analog IP, and hard macros; manage blockage and halo constraints to minimize routing congestion.
• Drive floorplan-driven synthesis feedback loops with the synthesis team; iterate on netlist placement to reduce post-route timing and congestion surprises.
• Power Planning & Power Delivery Network (PDN)
• Design and implement the on-chip power delivery network — power rings, power straps, and rail routing — to meet IR drop and electromigration (EM) targets.
• Coordinate with power analysis teams on static and dynamic IR drop budgets; iterate on PDN to achieve sign-off across all power domains.
• Implement and validate multi-voltage domain power structures per UPF/CPF — power switches, isolation cells, level shifters, and always-on logic placement.

Who can apply

• B.Tech / M.Tech / M.S. in Electronics Engineering, VLSI Design, Computer Engineering, or a related field with
• 10+ years in physical implementation, floorplanning, or place-and-route roles
• Expert-level proficiency with Cadence Innovus and/or Synopsys ICC2 / Fusion Compiler
• Strong experience in die-level floorplanning, macro placement, and PDN design
• Hands-on clock tree synthesis (CTS) experience across high-frequency, multi-clock designs
• Expertise in timing-driven physical closure and ECO-based hold/setup fixing
• Familiarity with physical verification tools (IC Validator, PVS) and DRC/LVS sign-off
• Working knowledge of synthesis (Fusion Compiler) and STA (PrimeTime)
• Proficiency in Tcl; Python scripting a strong plus
• At least one tape-out on 7nm or below

About Ericsson

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