Principal Digital Engineer (DFT Design)

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Skills you'll use

What you'll do

• Inserting DFT/Scan on digital logic, ATPG, validating test patterns on pre and post layout gate level netlist.
• Delivering test patterns to TEST engineering team and validating them on silicon.
• Inserting Logicbist with industry standard tools.
• Improving scan coverage and modifying RTL for scan.
• Reduce ATE tester time by reducing scan patterns while achieving the required coverage.
• Participate in all aspects of digital design flow - Micro-architecture, Design partitioning, RTL Verilog / System Verilog coding, DFT insertion, generating Timing Constraints, Synthesis, Interaction with P&R Team, Timing Analysis, LINT, CDC.
• Working closely with Architects, Design, P&R, Test and Silicon validation teams.
• Assisting with top level test-bench creation for scan and running gate level simulations.

Who can apply

• Debug scan pattern fails on ATE and fix the scan patterns.
• Writing detailed design documents and help writing DFT specifications, reviewing the specs with different stake holders and own the design to meet the spec.
• Organizing and participating in key design reviews and completion of various checklists.
• Masters plus 12+ years or Bachelors plus 15+ years experience in digital design and DFT implementation.
• Must be a team player and yet be an independent thinker with strong digital design and DFT fundamentals
• Hands on experience in Scan insertion, improving scan coverage, ATPG, experience in Logicbist insertion during synthesis or rtl.
• Gate level simulations with test patterns, delivering test patterns to Test engineering team and work closely with them to get the patterns validated. 
• Must have basic digital RTL coding experience besides synthesis exposure.

About Renesas Electronics

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