VLSI Design Intern at Siemens

About this internship

Skills you'll use

What you'll do

• Write and simulate RTL modules in Verilog/VHDL.
• Run functional verification against test benches.
• Support timing and synthesis analysis on blocks.
• Document design intent and verification results.
• Document your work so the next person can pick it up

Who can apply

• Education: pursuing or completed B.E./B.Tech/M.Tech in Electronics, Electrical, VLSI or a related discipline
• Graduation year: 2025, 2026 or 2027 batch
• Minimum 60% / 6.0 CGPA (relaxable for candidates with strong practical projects)
• Technical skills: working knowledge of VLSI, Verilog, VHDL, Digital Design
• Soft skills: clear written communication, ownership, willingness to document work
• Experience: none required — freshers welcome; prior projects or certifications are a plus

Perks & benefits

Interview & selection process

1. 1The selection process for the VLSI Design Intern role at Siemens is merit-based and typically runs over 4 stages: Round 1: Application & Resume Screening — apply through this page; profiles are shortlisted on fundamentals, projects and role fit. Round 2: Online Assessment — aptitude plus role-specific questions covering VLSI, Verilog, VHDL. Round 3: Technical / Functional Interview — a discussion of your projects and practical scenarios covering VLSI, Verilog, VHDL, Digital Design, RTL. Expect "how would you approach this?" rather than definitions. Round 4: HR Discussion — role expectations, stipend, start date, location and offer. Shortlisted candidates are contacted after applying. There are no charges at any stage of the process — Siemens never asks candidates for money.

About Siemens

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