Physical Design Engineer

About this role

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Skills you'll use

What you'll do

• Execute block-level physical design from synthesized netlist to GDSII:
• Floorplanning and power grid design
• Placement and optimization
• Clock Tree Synthesis (CTS)
• Routing and post-route optimization
• Drive timing convergence across MCMM scenarios in collaboration with STA teams
• Ensure design closure including:
• Setup/hold timing closure
• DRC/LVS clean signoff
• IR drop and electromigration (EM) compliance

Who can apply

• Bachelor’s/Master’s degree in Electronics / Electrical Engineering / Microelectronics
• 3–5 years of experience in ASIC Physical Design
• Strong understanding of:
• Physical design flow (FP → P&R → Signoff)
• Static Timing Analysis fundamentals
• CMOS digital design basics
• Hands-on experience with industry EDA tools:
• Cadence (Innovus/Genus) or Synopsys (ICC2/Fusion Compiler, PrimeTime)
• Good scripting skills in Tcl, Python, or Shell
• Experience in advanced nodes (16nm and below)

About NXP

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