Senior Engineer - ASIC Backend Synthesis

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Skills you'll use

What you'll do

• Physical-Aware Synthesis (PAS)
• Execute physical-aware and floorplan-driven synthesis flows to minimize post-layout timing and congestion surprises.
• Integrate synthesis with P&R tools for early physical feedback loops — congestion-aware optimization, placement-aware buffering, and pre-CTS timing.
• Collaborate with P&R engineers on DEF/floorplan hand-off; iterate on netlist quality to reduce downstream ECO effort.
• Perform flat and hierarchical synthesis for large designs; manage partitioning and interface timing budgets.
• Perform formal or equivalence check on the netlist at block or top level.
• QoR & Optimization
• Track and report key QoR metrics — timing slack, area, cell count, power — across design iterations and process corners.
• Identify and resolve synthesis bottlenecks: critical path restructuring, datapath optimization, and register retiming.
• Provide RTL coding guideline feedback to design teams to improve synthesizability and QoR from the source.

Who can apply

• 8+ years in physical synthesis or logic design implementation
• Expert-level use of Fusion Compiler
• Strong SDC constraint authoring and management skills
• Experience with physical-aware synthesis flows and P&R hand-off
• Working knowledge of STA (PrimeTime)
• Proficiency in Tcl; Python scripting a strong plus
• At least one tape-out on 7nm or below

About Ericsson

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