VLSI Design Engineer Intern

About this internship

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Skills you'll use

What you'll do

• Work on writing and verifying RTL for real silicon blocks alongside the core team
• Apply Verilog / SystemVerilog, RTL Design, ASIC / FPGA Architecture, Cadence / Synopsys Tools to live, production-facing problems
• Document your work clearly for reviewers and stakeholders
• Participate in reviews and act on the feedback you receive
• Collaborate across engineering, product, design or business as required
• Follow the team's quality, testing and documentation standards

Who can apply

• Pursuing or recently completed B.E./B.Tech (ECE/EEE/E&I), M.Tech (VLSI / Microelectronics) or M.Sc (Electronics) — 2026 freshers & final-year students welcome
• Working knowledge of Verilog / SystemVerilog, RTL Design, ASIC / FPGA Architecture (or a genuine willingness to learn them)
• Strong fundamentals in your discipline and clear problem-solving ability
• Care with detail and the discipline to document your work
• Clear written and verbal communication in English
• Based in or willing to work from Udaipur, Rajasthan

Perks & benefits

Interview & selection process

3 rounds — typical selection flow for this role:

1. 1Application screening & resume shortlisting by the talent team
2. 2Team-fit / behavioural interview with the team
3. 3HR discussion — stipend, start date, expectations and offer

About Tejas Networks

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