VLSI Design Intern

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Skills you'll use

What you'll do

• Work on RTL, verification and timing closure — where a design is not done until it meets constraints alongside the core team
• Apply Verilog, VHDL, RTL Design, Digital Electronics to live, production-facing problems
• Document your work clearly for reviewers and stakeholders
• Participate in reviews and act on the feedback you receive
• Collaborate across engineering, product, design or business as required
• Follow the team's quality, testing and documentation standards

Who can apply

• Pursuing or recently completed B.E./B.Tech (ECE/EEE/Electronics/Instrumentation) or M.Tech (VLSI / Embedded Systems)
• Graduating batch 2026 or 2027 — final-year students and recent graduates welcome
• 60% / 6.0 CGPA and above preferred; strong project work is considered alongside academics
• Working knowledge of Verilog, VHDL, RTL Design (or a genuine willingness to learn them)
• Exposure to Digital Electronics, Cadence or Synopsys Tools, Functional Verification is an advantage
• Clear written and verbal communication in English, and care with detail in your work
• No prior work experience required — this is a fresher-friendly internship
• Based in Jharsuguda, Odisha or willing to work from there for the internship period

Perks & benefits

Interview & selection process

3 rounds — typical selection flow for this role:

1. 1Application screening & resume shortlisting by the talent team
2. 2Online aptitude / domain assessment
3. 3HR discussion — stipend, start date, expectations and offer

About Sigmoid Analytics

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