VLSI Design Intern

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Skills you'll use

What you'll do

• Work on writing RTL and verifying it, where a bug found after tape-out costs a great deal more than one found now alongside the core team
• Apply Verilog, SystemVerilog, RTL Design, Functional Verification to live, production-facing problems
• Document your work clearly for reviewers and stakeholders
• Participate in reviews and act on the feedback you receive
• Collaborate across engineering, product, design or business as required
• Follow the team's quality, testing and documentation standards

Who can apply

• Pursuing or recently completed B.E./B.Tech (ECE/EEE/VLSI), M.Tech (VLSI/Embedded) or M.Sc (Electronics)
• Graduating batch 2026 or 2027 — final-year students and recent graduates welcome
• 60% / 6.0 CGPA and above preferred; strong project work is considered alongside academics
• Working knowledge of Verilog, SystemVerilog, RTL Design (or a genuine willingness to learn them)
• Exposure to Functional Verification, Testbench Development, Digital Electronics is an advantage
• Clear written and verbal communication in English, and care with detail in your work
• No prior work experience required — this is a fresher-friendly internship
• Based in Hyderabad, Telangana or willing to work from there for the internship period

Perks & benefits

Interview & selection process

3 rounds — typical selection flow for this role:

1. 1Application screening & resume shortlisting by the talent team
2. 2Online aptitude / domain assessment
3. 3HR discussion — stipend, start date, expectations and offer

About Ideaforge Research

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