RTL Design Intern

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Skills you'll use

What you'll do

• Work on writing synthesisable RTL and proving it meets timing before anyone taps out a chip alongside the core team
• Apply Verilog, SystemVerilog, RTL Coding, Synthesis to live, production-facing problems
• Document your work clearly for reviewers and stakeholders
• Participate in reviews and act on the feedback you receive
• Collaborate across engineering, product, design or business as required
• Follow the team's quality, testing and documentation standards

Who can apply

• Pursuing or recently completed B.E./B.Tech/Diploma in Electronics, Electrical, E&TC or Instrumentation Engineering
• Graduating batch 2025, 2026 or 2027 — final-year students and recent graduates welcome
• 60% / 6.0 CGPA and above preferred; strong project work is considered alongside academics
• Working knowledge of Verilog, SystemVerilog, RTL Coding (or a genuine willingness to learn them)
• Exposure to Synthesis, Static Timing Analysis, Simulation is an advantage
• Clear written and verbal communication in English, and care with detail in your work
• No prior work experience required — this is a fresher-friendly internship
• Based in Pimpri-Chinchwad, Maharashtra or willing to work from there for the internship period

Perks & benefits

Interview & selection process

4 rounds — typical selection flow for this role:

1. 1Application screening & resume shortlisting by the talent team
2. 2Discussion with the hiring manager on the role and your fit
3. 3Team-fit / behavioural interview with the team
4. 4HR discussion — stipend, start date, expectations and offer

About Edgistify

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