Location
Una, Himachal Pradesh
Work Mode
Hybrid
Duration
3 months
Stipend
₹22,000/mo
Start Date
Immediate / Rolling
Openings
3 positions
Type
Full-time
Category
Engineering
About the Internship
Idealabs is hiring a VLSI Design Intern in Una — a hands-on, mentor-led internship built for students and 2026 freshers who want real exposure to VLSI design rather than a certificate-only programme.
About the role
As a VLSI Design Intern at Idealabs, your core focus will be RTL, verification and…
About Idealabs
Idealabs offers a mentor-led VLSI Design Intern in Una with live project work in engineering, a stipend of ₹22,000/month and a Pre-Placement Offer opportunity for strong performers.
See all Idealabsinternships →Una, Himachal PradeshVerified employer3 openings
Apply to Idealabs →Skills Required
VerilogVHDLRTL DesignDigital ElectronicsCadence or Synopsys ToolsFunctional VerificationStatic Timing AnalysisFPGA BasicsSystemVerilogTechnical Documentation
Who Can Apply
- Final-year students and recent graduates from B.E./B.Tech (ECE/EEE/Electronics/Instrumentation) or M.Tech (VLSI / Embedded Systems) who are based in or willing to work from Una. You should be keen to learn Verilog, VHDL, RTL Design on real projects and able to write clearly. Freshers are welcome — no prior work experience is required, and a strong project portfolio matters more than a long CV.
Perks
Internship CertificateLetter of RecommendationMentorship from a named mentorLive project experienceExposure to professional tools and workflowsDirect access to the team that owns the data you work on
Interview & Selection Process
3 rounds — typical selection flow for this role:
- 1Application screening & resume shortlisting by the talent team
- 2Team-fit / behavioural interview with the team
- 3HR discussion — stipend, start date, expectations and offer
₹22,000/month
Stipend · 3 months
Openings3 positions
Applicants0 applied
ModeHybrid
CategoryEngineering
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